The performance of small transistors, such as MOSFETs, can be affected by a short-channel effect commonly referred to as “punchthrough.” Punchthrough can be observed when a depletion region generated, for example, by the drain region of a MOSFET, contacts or comes into close proximity with an opposing depletion region generated by the opposing source region of the MOSFET. The contact of the depletion regions can cause charge to transfer between the source and drain region regardless of the voltage supplied to the gate. Therefore, MOSFETs affected by punchthrough may lose the ability to function as a switch (i.e,. to turn off completely).
It is known to compensate for the effects of punchthrough by implanting impurity ions into the substrate of the MOSFET. FIG. 1 is a graph that illustrates exemplary effects of implants in the substrate of a short channel MOSFET. In particular, curve (a) of FIG. 1 illustrates that punchthrough can develop in a MOSFET, without an ion implant, when the channel length of the MOSFET is reduced to about 0.85 μm. In contrast, curves (b) and (c) of FIG. 1 illustrate that an ion implantation into the substrate at respectively increasing dosages can suppress the onset of punchthrough until the channel length is reduced to a length approaching 0.5 μm.
FIG. 2 illustrates a MOSFET having a punchthrough region implant 200 in the substrate which can block a depletion region 205 generated, for example, by the source region, from reaching the drain region or a depletion region generated by the drain region. Accordingly, the punchthrough region implant 200 may prevent the onset of punchthrough so that the MOSFET can continue to operate reliably despite having a short channel length which might otherwise be subject to punchthrough. The following patents may be relevant to the present disclosure: U.S. Pat. No. 5,614,430 to Liang et al., entitled Anti-Punchthrough Ion Implantation for Sub-half Micron Channel Length MOSFET Devices; U.S. Pat. No. 5,766,998 to Tseng, entitled Method for Fabricating Narrow Channel Field Effect Transistors Having Titanium Shallow Junctions; U.S. Pat. No. 6,268,256 to Kuo, entitled Method for Reducing Short Channel Effect; and U.S. Pat. No. 6,285,061 to Shell et al., entitled Structure and Method for Fabricating a Field Effect Transistor with a Self-Aligned Anti-Punchthrough Implant Channel. Additional information relating to punchthrough and punchthrough implants may also be found in Wolf, S., Silicon Processing for the VLSI Era Volume 2: Process Integration, Sunset Beach, Calif., 1990.